(a) Field of the Invention
The present invention relates to a mask for use in a projection electron beam exposure and, more particularly, to a projection exposure mask capable of forming a uniform pattern on a semiconductor wafer by correcting a proximity effect.
(b) Description of the Related Art
With the development of LSIs, the line pattern formed on the semiconductor device has become rapidly finer and finer. An electron beam exposure technique is expected to provide a finer pattern designed with as low as 0.25 .mu.m design rule in the next generation semiconductor devices.
FIG. 1 shows a known projection electron beam exposure system in a block diagram. The projection exposure system comprises a first mask 3 having a rectangular opening 3A for passing a rectangular electron beam 50A and a second mask 6 having a patterned opening in the area aligned with the rectangular opening 3A of the first mask 3 for passing a patterned electron beam 50B. The patterned electron beam 50B passed by the second mask 6 is irradiated onto the surface of a semiconductor wafer 11 to transfer the pattern 6B of the second mask 6 in a reduction projection scheme onto the surface of the semiconductor wafer 11 applied with a resist film thereon. The first mask 3 functions for defining the size of the electron beam used for a single exposure step, wherein the size of the electron beam 50A is slightly larger than the area for the pattern of the second mask 6.
The second mask 6 used for fabrication of a memory device, wherein a unit pattern is iteratively formed in the whole cell area, generally has a size corresponding to the size tor the unit pattern. The patterned electron beam 50B passed by the second mask 6 forms a latent image in the unit area on the resist mask in a single exposure step.
Alternatively, the second mask 6 may have a plurality of unit patterns, such as 6A to 6E shown in FIG. 2, which are derived from the design data for an LSI. Or, the size of the patterned area may correspond to the chip of the LSI, wherein the second mask has a single patterned opening for the entire chip area of the LSI.
Back to FIG. 1, the electron beam 50 emitted from an electron gun 1 passes through a blanking electrode 2, the first mask 3, a shaping lens 4, a shaping deflector 5, the second mask 6, a reduction lens 7, a main deflector 8, an auxiliary deflector 9 and a projection lens 10 to be incident onto the semiconductor water 11 fixed on a stage 12. The patterned electron beam 50B passed by the second mask 6 is reduced in size by the reduction lens 7, deflected by the main deflector 8 and the auxiliary deflector 9 to be incident onto the specified portion of the semiconductor wafer 11.
The computer (CPU) 14 selects a specified pattern data out of a plurality of pattern data stored in a pattern data storage device 17, stores the selected pattern data in a memory 17, and operates for processing using the stored data. Specifically, the stored data is transferred from the CPU 14 through a controller 16 to the blanking electrode 2, shaping deflector 5, main deflector 8 and auxiliary deflector 9 for irradiating the patterned electron beam 50B onto the specified portion of the semiconductor wafer 11.
The electron beam exposure system as described above has an advantage over the conventional electron beam exposure system using a variably shaped electron beam in that the number of beam shots is reduced down to 1/10 or 1/100 compared to the conventional electron beam exposure system. As a result, the time length necessary to the exposure is reduced to improve the throughput of the exposure.
FIG. 3 shows an example of a unit pattern 20 iteratively transferred onto a semiconductor wafer by using the opening pattern 6A in the second mask of FIG. 2 to form a memory cell array 18. In this process, there arises a defect called "proximity effect" wherein the pattern density difference involved between the central part and the peripheral area of the cell array 18 provides different pattern dimensions between the central part and the peripheral part of the photoresist due to the change in the exposure intensity from adjacent openings.
FIG. 4 shows the relationship between the width (L.sub.1 in FIG. 3) of a line in the photoresist pattern and the distance of the location of the line from the edge of the cell array. For example, the exposure mask which provides a width of 0.2 .mu.m for a line in the central area of the cell array provides a width as low as 0.1 .mu.m in the peripheral area. Since the exposure intensity is not generally changed in the projection exposure process, the proximity effect involves a critical problem.
Patent Publication JP-A-4-26012 proposes to solve the proximity effect in the projection exposure process for a semiconductor chip by changing the pattern size in the second mask. FIG. 5A shows a plurality of unit patterns in the second mask proposed by the publication, and FIG. 5B shows the cross-section taken along line B--B in FIG. 5A. The proposed mask 26 has a larger size in some of the unit patterns 26A used for the peripheral area of the cell array compared to the unit pattern 26B used in the central area of the cell array.
It involves a complicated procedure, however, to select one of the unit patterns 26A and 26B depending on the location of the electron beam in the exposure step using the proposed exposure mask 26.
Patent Publication JP-A-5-335221 proposes another solution for the proximity effect, as shown in FIG. 6, wherein a main pattern 36A and an auxiliary pattern 36 B are formed on a single second mask 36. An auxiliary exposure or GHOST exposure is effected, after a main exposure step, by using the auxiliary pattern 36B having a zone opening for exposing the peripheral area of the chip.
The proposed technique, however, increases the number of exposure steps to thereby reduce the through-put of the exposure.